Building 3D stacked architectures with interlayer cooling
Profs. John R. Thome and David Atienza ~ Project Website
The CMOSAIC project is a genuine opportunity to contribute to the realization of arguably the most complicated system that mankind has ever assembled: a 3D stack of computer chips with a functionality per unit volume that nearly parallels the functional density of a human brain.
CMOSAIC endeavours to maintain the overall pace according to Moore’s law requires an acceleration of packaging development according to recent ITRS reports. Beneficially for the IT industry, mobile device companies have driven 3D packaging development in the past few years but thermal aspects and high density interconnects have been neglected in those applications. While 2D scaling has been used in high performance processors over several decades, the third dimension has not yet been tackled.
Recent progress in the fabrication of through silicon vias (TSV) has opened new avenues for high density area array interconnects between stacked processor and memory chips. Such 3 Dimensional-Integrated Circuits (3D-ICs) are extremely attractive for overcoming the barriers in interconnect scaling, offering an opportunity to continue the CMOS performance trends for the next decade. By integrating a very large System on a Chip (SoC) in multiple tiers, the average distance between system components is reduced, which in turn will improve the performance, but the challenge to remove the heat is multiplied by the number of layers in the integration of the micro-cooling channels between the silicon vias. The reason is that SoCs dissipate on average about 50-100 W/cm2, which is already challenging on 2D spread out substrates.
It is thus safe to claim that “the future of 3D stacked SoCs crucially depends on providing practical solutions for heat removal”.
In CMOSAIC, a multi-disciplinary team jointly conduct experimental research, develop the necessary modeling tools, simulate 3D-IC stacks and test various prototype stacks to develop practical methods for heat removal in high performance 3D-ICs.are known, the entire 3D-IC stack temperature distribution together with its cooling elements is calculated, including thermal stresses. For the architecture design, modeling at the circuit level, fabrication of the 3D stack and thermal simulations of the microprocessor heat flux “footprints”, the LSM and ESL of the EPFL and our industrial partner IBM are world leading specialists.
This project addresses the aspect of system integration with two orders of magnitude higher complexities, represented by going from 2D to 3D and from the linking of local IC heat generation to local heat dissipation, and by developing the fundamental understanding, methods and tools required for efficient and reliable design of true 3D systems. Furthermore, it will achieve the research objectives of the Nano-Tera.ch program in the field of micro/nano-electronics and the integration of these technologies into high performance computing. Additionally, the proposal specifically matches the Nano-Tera.Ch program’s desired characteristics: engineering of complex (tera) systems out of small (nano/micro) components, by leveraging scientific and technological discoveries, with the objective of developing technology demonstrators that can be transformed into products in the medium term, incorporating various disciplines through well coordinated research efforts to explore the proposed topics at the boundary of traditional scientific domains and benefiting the earth, security and environment.
Overall, from a global perspective, CMOSAIC addresses the vertical axis of micro/nanoelectronics, particularly the aspect of system integration. Specifically, the results of this project will be a significant step toward “achieving system complexities that are two-to-three orders of magnitude higher than today’s state-of-the-art”, by developing the fundamental understanding, methods and tools required for efficient and reliable design of true 3D integrated circuits systems.