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Dynamatic

From C/C++ to Dynamically Scheduled Circuits

High-Level Synthesis (HLS) tools generate hardware designs from high-level programming languages.

Typically, these tools rely on static scheduling: the cycle in which each operation executes is fixed at compile time. This scheduling approach results in high-throughput pipelines in particular classes of applications. However, when memory accesses are unpredictable or control flow is irregular, standard HLS tools need to make pessimistic scheduling assumptions and produce suboptimal schedules. On the other hand, dataflow circuits implement dynamically scheduled circuits, in which components communicate locally using a handshake mechanism and exchange data as soon as all conditions for a transaction are satisfied. Due to their ability to adapt the schedule at runtime, dataflow circuits are suitable for handling irregular and control-dominated code.

Dynamatic is an academic, open-source high-level synthesis compiler that produces synchronous dynamically-scheduled circuits from C/C++ code. Dynamatic delivers significant performance improvements compared to state-of-the-art commercial HLS tools in applications with variable latencies of particular memory access patterns and control-flow decisions. In its current implementation, Dynamatic directly targets Xilinx FPGAs, and is customizable and extensible to target different hardware platforms.

To achieve high-throughput, pipelined hardware designs which meet the desired clock period, Dynamatic employs a performance optimization model which allows for resource-optimal buffer placement and sizing. Dynamatic supports out-of-order memory accesses by employing load-store queues (LSQs) at the memory interface; whenever the compiler can disambiguate memory accesses, groups of accesses that cannot mutually conflict use separate LSQs, while accesses that have no dependences with any other accesses are connected directly to memory. Dynamatic’s dynamically scheduled circuits open doors to new HLS features, such as speculative execution; such features are crucial for HLS to be successful in broad application domains.

Dynamatic is publicly available for download from https://dynamatic.epfl.ch/ and the source code is in GitHub.

Suggested Reading

https://dynamatic.epfl.ch/papers/FPGA_20_Dynamatic_From_C_C_to_Dynamically_Scheduled_Circuits.pdf
https://dynamatic.epfl.ch/