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Exploration of RRAM-Based Memory Solution for Edge Systems

RRAM is a promising solution due to its scalability and CMOS compatibility.

Edge computing devices utilize complex machine learning algorithms, which place a lot of stress on crucial factors like memory capacity, processing capability, and energy efficiency. In the search for new computing and memory technologies and architectures, researchers are exploring the options of using Functionality Enhanced Devices (FED) and emerging resistive memory technologies (RRAM) such as filamentary-based RRAM. The latter is already on the market and provides easy technology co-integration with MOS technologies, middle programming voltage, and fast switching capabilities.

RRAM is a promising solution due to its scalability and CMOS compatibility, which enables the fabrication of high-density RRAM crossbar arrays in Back-End-Of-Line CMOS processes. However, fast and accurate architectural models of RRAM crossbar devices are required to perform system-level design space explorations of new Storage Class Memory (SCM) architectures using RRAM. To address that challenge, we developed RRAMSpec, an architecture design space exploration framework, which enables fast exploration of various architectural trade-offs in designing high-density RRAM devices, at accuracy levels close to circuit-level simulators.

An inherent problem in RRAM technologies is a strong device-to-device and cycle-to-cycle variability, which worsens by age. To address that challenge, we propose the RRAM Variability Aware Controller (RRAM-VAC), which stores and then coalesces the write requests from the processor before triggering the actual write process. By doing so, it averages the RRAM variability and enables the system to run at the memory programming time distribution mean rather than the worst-case tail. We explore the design space of the proposed solution for various RRAM variability specifications, benchmark the effect of the proposed memory controller with real application memory traces and show (for the considered RRAM technology specifications) 44% to 50 % performances improvement and from 10% to 85% energy gains depending on the application memory access patterns.

In yet another related research, we proposed an industrially-ready WT circuit simulated with an RRAM model calibrated on real measurements. We simulated the effects of the WT circuit with memory traces extracted from real Edge-level data-intensive applications and demonstrated 2x to 40x of energy gains at bit level. We also showed 1.9x to 16.2x energy gains with real applications running, depending on the application memory access pattern.

Suggested Reading

https://link.springer.com/chapter/10.1007/978-3-030-27562-4_3
https://infoscience.epfl.ch/record/270463
https://infoscience.epfl.ch/record/277898?ln=en
https://infoscience.epfl.ch/record/272717
https://infoscience.epfl.ch/record/262758
https://infoscience.epfl.ch/record/265205