Integrated Power Delivery and Cooling Control
for 3D chips using Flow Cell Arrays (FCAs)
As we penetrate the sub-micron era, sub-threshold leakage and global interconnect delays have become a major bottleneck for both power and performance. Three-dimensional (3D) IC stacking is an attractive path to overcome the interconnect scaling issues and allow the integration of different technologies in a single heterogeneous chip. However, the 3D IC stacking technology is not widely used because of lack of design guidelines, test methods, tools, and equipment. 3D integration also faces many technical challenges. Researchers are proposing effective design solutions and methods to efficiently benefit from the 3D integration advantages. Such efforts are needed for 3D stacking to become widespread in the IC design industry.
We aim to address two major challenges of 3D integration, namely heat removal and power delivery of vertically stacked dies. To the best of our knowledge, we are the first research group to propose a combined cooling and on-chip power generation/delivery method for 3D stacked ICs. We have developed PowerCool a simulation tool to model the steady-state operation of a 3D SoC with integrated flow cell arrays (FCAs) technology. The FCAs, which consist of several inter-tier micro-channels filled with an electrolytic solution, are placed in the silicon substrate of each die. They provide liquid cooling to the 3D chip, while electrochemical reactions simultaneously take place between the electrolytes, to generate electrical power. This power can be directly supplied to the active circuit in the same die, or delivered to nearby dies via dedicated TSVs and microbumps. A continuous flow of the electrolytic liquid ensures a steady cooling and energy supply for the stacked dies.
This project focuses on the study, development, testing, and validation of the FCA technology. We demonstrate the accuracy of the electro-chemical model by comparing its results with the actual micro-scale flow cell. Another key area of the project is to qualitatively analyze the impact of FCAs on 3D SoCs and compare its performance against conventional air-cooled 2D technology and 3D chips without micro-fluidic channels. We model different 3D stack architectures, including processing units and memories. We also evaluate the heat-removal and the power generation capabilities of the FCAs for different 3D chip models using our PowerCool simulator, which combines electro-chemical and thermal simulations to output full system state for a given set of control and design parameters.